Image sensors comprise an array of unit elements, called pixels. The array of pixels is exposed to radiation during an exposure period and, subsequently, the signal value of each pixel is read from the array. The array can be a one dimensional array (linear sensor) or a two dimensional array (area array) with pixels arranged in rows and columns.
FIG. 1A shows the typical architecture of a CMOS image sensor and FIG. 1B shows a typical four transistor (4T) pixel which can be used for each of the pixels. Impinging photons are converted into charges in the pixel array 10 and are accumulated during an integration period, also known as an exposure period. Typically, these pixels are selected by row for readout of their signals. The pixel includes a photodiode PD, a transfer gate to transfer the charge in the photodiode to the floating diffusion FD, a reset transistor M1, a source follower M2 and a row selection transistor M3. The reset transistor M1 is used to reset the floating diffusion FD to a known state before transferring charge from the photodiode PD to the floating diffusion FD, as known in the art. The source follower M2 converts the charges stored at the floating diffusion FD into an electrical output voltage signal at the column bus. The useful signal outputs of a pixel are analog voltages representing: (i) the reset signal level Vreset and (ii) the signal level Vsig that is generated after charge transfer from the photodiode PD. A desired output signal, which represents the amount of photons impinged onto the pixel during the integration period, is the difference between the reset signal level Vreset and the signal level Vsig. In the sensor of FIG. 1A, there is sample and hold circuitry 15 associated with each column of the array. During the process of reading the array, the sample and hold circuitry 15 for each column stores the two signal values (Vreset, Vsig) for a pixel in a selected row. The two signals (Vreset, Vsig), or the difference between these signals (Vreset−Vsig), is converted from an analog value to a digital value. In FIG. 1A the analog-to-digital conversion is performed by a single ADC 16 in the output stage of the array and this single ADC 16 is used, on a time-shared basis, by the column circuits. In turn, signal values are transferred from each of the column circuits to the ADC 16 and converted to digital form.
Various arrangements have been proposed where analog-to-digital conversion is performed, in parallel, in an output stage of each column of the array. FIG. 2 shows an arrangement with a single-slope ADC comprising a ramp generator 20 and a synchronous counter 17. Each column has two data latches 18 and a comparator 19. A ramp signal is applied to each of the columns circuits. The ramp signal is distributed to all columns. The counter 17 is incremented in synchronism with the ramp signal such that, at any point in time, the counter 17 provides a digital representation of the analog value of the ramp signal output by the ramp generator 20. The comparator 19 in each column compares the level of the input signal (Vreset or Vsig) against the gradually changing ramp signal. When the ramp voltage reaches the value of the input signal voltage, the comparator 19 output changes state and latches the digital code of the counter into a first memory 18. Afterwards, the same process is repeated for the other of the signals (Vreset, Vsig) and the code is latched into a second memory 18. The difference in digital codes is then sent to the output of the sensor.
Refinements of this arrangement are described in U.S. Pat. No. 7,088,279, U.S. Pat. No. 7,321,329, EP application 2 048 786 A2. As shown in FIG. 3, the circuitry 30 associated with each column is provided with a single dedicated bi-directional counter 31. The counter performs a count in one direction during a first conversion cycle, and a count in the other direction during a second conversion cycle. Other refinements are described in U.S. Pat. No. 7,880,662, U.S. Pat. No. 8,253,617 and U.S. Pat. No. 8,253,616 and are depicted in FIG. 4. The circuitry 30 associated with each column is provided with a single dedicated uni-directional counter 32. An example of timing of FIG. 4 is shown in FIG. 5. In this case, two conversion cycles are used. The counter is activated during the first conversion cycle when the ramp signal reaches the reset level and counts until the end of the ramp cycle. During a second conversion cycle, the counter is activated between the start of the ramp signal and when the ramp signal reaches the signal level. The value held in the counter at the end of the second conversion cycle is proportional to the difference between the signal level and reset level. This architecture has some advantages compared to more conventional architectures. Column-to-column variations of clock skew and counter delay which cause A/D conversion error can be corrected for.
A further refinement of this architecture targeted to faster conversion speeds is described in U.S. Pat. No. 8,040,269. Two counters are used inside each column. The counters run at a high frequency which is locally generated inside the column and which can vary from column to column. To avoid conversion errors due to variations in frequency between the columns, two counters are used. Two differential values can be determined by use of both counters. A first differential value corresponds to the difference between the signal and reset level. A second differential value corresponds to the difference between two reference levels which are common for all columns. The ratio of the two differential values is representative for the difference between the signal and reset level, and is not affected by the variations in clock frequency.